1. Field of the Invention
The invention relates generally to the field of methods for fabricating integrated circuit chips using MOSFET (metal oxide semiconductor field effect transistor) technology or, more generally, insulated gate field effect transistor integrated circuit chips and to integrated circuit chips produced thereby.
2. Description of the Prior Art
The process of manufacturing an MOSFET or IGFET integrated circuit chip can be generally divided into two general sequences of steps. First, the active areas are defined on the substrate by growing or depositing field oxide insulation in the areas of the substrate surrounding the active device areas, that is, the areas of the chip on which the active components such as transistors are to be fabricated. These active areas are left free of the oxide insulation layer. Typically, a field implant is provided under the field oxide to eliminate surface inversion problems in the substrate. During the second portion of the semi-conductor processing, the circuit components, that is, the transistors and other circuit elements, are defined, fabricated and interconnected by metal or polysilicon film strips deposited over the field oxide.
Two general techniques have been used in the first sequence, that is, the field oxide and implant sequence. In one technique, which results in a chip generally described as "non-isoplanar", an ion implant bombards the upper surface to provide a field implant and a layer of oxide is grown over the entire upper surface of the chip at high temperature in a steam atmosphere. The ions, typically boron if the substrate is a P-type substrate, impregnate the entire upper surface of the substrate under the oxide. The active regions are then defined by a photo-resist, and the oxide in the active regions is removed. A compensation implant, which is required to neutralize the portion of the field implant in the active areas, is then deposited in the exposed upper surface of the substrate. With this procedure, the channels of the IGFET transistors will be buried in the substrate, rather than being adjacent the surface. A surface channel IGFET is generally more desirable than a buried channel IGFET. Furthermore, since the field oxide is grown at high temperature, the field implant will expand into the substrate during field oxide growth. Accordingly, the peripheral areas between the field implant and the source and drain regions will be relatively large, resulting in a relatively high peripheral junction capacitance between the sides of the source and drain regions and the field implant, which results in slower operation of the transistors.
The second general technique for providing the field oxide and implant, called the "local oxide" or "LOCOS" process, has been developed which results in a significantly more planar device than the other technique. The local oxide technique results in the upper surface of the field oxide being at or near the same level as the level of the substrate in the active regions. In the local oxide technique, the initial oxide layer is deposited on the entire surface of the substrate, and a silicon nitride layer is deposited thereover. The active regions are then defined by a photo-resist, and the silicon nitride in the field regions outside of the active regions is removed. The field implant is then produced by bombarding the chip surface with boron ions, as in the non-isoplanar technique; however, the silicon nitride and remaining photo-resist in the local oxidation technique shields the substrate from the ions and so the field implant is produced only in the field regions outside of the active regions. The chip is then placed in a steam atmosphere at high temperature and the oxide layer, in the field regions not shielded by the silicon nitride, grows to a desired thickness for the field oxide. The photoresist, nitride, and initial oxide in the active region are then removed.
In the local oxidation technique a surface channel device is produced, but the technique has several other deficiencies. First, since the field oxide is grown from the silicon in the substrate, the field region's thickness expands, while the active region does not. Accordingly, crystalline defects can result in the substrate which can result in device failure.
Furthermore, the silicon nitride can react with the silicon substrate under the edges of the initial oxide in the active regions, resulting in a "white ribbon" effect. In that reaction, the silicon nitride coating breaks down and the nitrogen therefrom reacts with the silicon in the silicon substrate along the edges of the initial oxide layer. All around the initial oxide layer, the underlying substrate, when the oxide is removed, exhibits a silicon nitride ribbon around the periphery of the device region, which, in turn, can result in failures in the gate oxide, such as ruptures at lower voltages than otherwise. Furthermore, as in the non-isoplanar technique, the high temperatures used in the field oxide growth step results in a deeper field implant, which, in turn, results in an increase in the peripheral area between the field implant and the source and drain regions, thereby causing an increased peripheral junction capacitance therebetween, which can, in turn result in a slower device operation.
Finally, the growth of the field oxide in the local oxidation technique also results in a horizontal encroachment of the field oxide into the active region. Thus, with this procedure, it is difficult to maintain accurate control over the width of the active device regions.
After the gate oxide insulation and gate electrode are formed on the surface of the substrate the source and drain regions of the active devices have been formed and the interconnections deposited. Generally, the interconnections are patterns of a polysilicon or metal film deposited on the field oxide and placed in physical and electrical contact with the source and drain regions and the other interconnecting lines. A problem may result, however, if metal is used to form the interconnects, since metal has poor step coverage over sharp corners which may be present. Therefore, it is desirable to have as planar a device as possible before the metal film is deposited. Since the top surface of the field oxide is generally at a much higher elevation than, for example, the surface of the source and drain regions, particularly in a non-isoplanar chip, it is apparent that connection problems may result during the formation of interconnections.
In view of the problems inherent in connecting the source and drain regions to the metal interconnection pattern over inclined surfaces and over corners on, for example, the field oxide, methods have been developed, exemplified in U.S. patent application Ser. No. 505,046 filed June 16, 1983, by the present inventor and assigned to the assignee of the present application, in which a chip, after the source and drain regions and the gate electrode are provided, is covered with an insulation layer which supports the interconnect pattern. Apertures are etched in the insulation layer to the source and drain regions and the polysilicon interconnects and filled with a conductive material. The metal interconnection pattern is then formed. If multiple interconnection layers are required, the process is repeated. However, since the level of the upper surfaces of the polysilicon interconnects are much higher than the level of the upper surface of the source and drain regions, the etching will expose the polysilicon interconnects before it exposes the source and drain regions, and the extra time required to expose the source and drain regions may result in damage to the polysilicon interconnects.
It often becomes necessary in the processing of an integrated circuit chip to fill in a recess in, for example, a dielectric such as an oxide layer with a metal conductor material. In the aforementioned U.S. patent application Ser. No. 505,046, a technique is described for performing this operation. In brief, a metal film is deposited by the surface of the chip. The depth of the film is sufficient to at least fill the recess in the dielectric and leave a recess in the upper surface of the metal film. A photoresist coating is applied over the metal film to fill the recess in the metal film and provide a planar upper surface. The photoresist coating is etched by reactive ion etching techniques, leaving the photoresist in the recess in the metal film. A metal etch is then applied, which removes the metal outside the recess. The remaining photoresist is then removed, leaving the metal in the recess. This technique is generally limited to filling recesses having widths of ten microns or less, on chips in which the recesses are of uniform widths. Thus, if the recesses are of significantly diverse widths or if they have widths of greater than about ten microns, the process described in the above-mentioned patent application may not provide satisfactory filling of the recesses.